IBM and Lam Research Partner to Break 1nm Barrier with High-NA EUV Dry Resist
Key Facts
- What: IBM and Lam Research launched a five-year collaboration to develop materials and processes for sub-1nm logic scaling using High-NA EUV lithography and Lam’s Aether dry resist technology.
- Where: Work will center at IBM’s Albany NanoTech Complex in New York.
- Focus: Full process flow validation for nanosheet and nanostack device architectures plus backside power delivery.
- Goal: Enable lower-power, higher-performance transistors critical for the AI era.
- Significance: Represents the next major step beyond current 2nm and 3nm nodes toward angstrom-scale logic.
Lead paragraph
IBM and Lam Research announced a five-year partnership to accelerate chip scaling below 1nm using High-NA EUV lithography and advanced dry resist technology. The collaboration will integrate Lam’s Aether dry resist into complete process flows for next-generation nanosheet and nanostack transistors with backside power delivery at IBM’s Albany research facility. The companies say the work is essential to deliver the power-efficient, high-performance silicon required to sustain AI training and inference demands in the coming decade.
Body
The partnership builds on years of prior cooperation between the two firms. Lam Research will supply its proprietary dry resist materials and High-NA EUV process expertise, while IBM contributes its leading device architecture research and Albany lab infrastructure. The Albany NanoTech Complex already hosts one of the world’s most advanced semiconductor research ecosystems, including ASML’s latest High-NA EUV tools.
High-NA EUV lithography represents the semiconductor industry’s most significant tooling leap in more than a decade. Traditional EUV systems operate at a numerical aperture (NA) of 0.33. High-NA systems increase that to 0.55, theoretically delivering 1.7× higher resolution. The improved optics allow chipmakers to print smaller features with fewer multi-patterning steps, but they also introduce new challenges around resist performance, stochastic effects, and process integration.
Lam’s Aether dry resist technology is designed to address many of these challenges. Unlike conventional wet photoresists, dry resists are deposited in a vapor-phase process, offering improved uniformity, higher sensitivity, and better etch selectivity. These characteristics become increasingly important at sub-1nm dimensions where even minor variations in resist thickness or line-edge roughness can destroy device yield.
According to the joint announcement, the teams will focus on validating full process flows rather than isolated tool or material improvements. This includes integrating High-NA EUV dry resist into nanosheet gate-all-around transistors, exploring vertical “nanostack” architectures, and incorporating backside power delivery networks that separate power rails from signal wiring to reduce congestion and improve efficiency.
IBM and Lam on the AI Imperative
Both companies explicitly tie the project to artificial intelligence demands. In a statement, Lam Research emphasized the strategic importance: “We are proud to build on our successful collaboration with IBM to drive High‑NA EUV dry resist and process breakthroughs, accelerating the development of lower power and higher performance transistors that will be critical for AI era.”
The quote underscores a growing industry consensus: continued transistor scaling is no longer optional if the exponential growth in AI compute requirements is to remain economically viable. Training and inference clusters already consume enormous amounts of power. Without meaningful improvements in performance-per-watt at the silicon level, data center operators face unsustainable energy costs.
Competitive Landscape
The IBM-Lam collaboration occurs against a backdrop of intensifying competition in advanced process development. TSMC has begun risk production on 2nm technology and is already planning A16 (1.6nm) with backside power delivery. Intel has committed to its 18A and 14A nodes using High-NA EUV, with the first High-NA tools already installed in its development fab. Samsung continues aggressive scaling with plans for sub-2nm offerings.
IBM itself exited consumer chip manufacturing years ago but maintains one of the industry’s most respected research organizations. The company’s nanosheet technology formed the foundation for Samsung’s 3nm process, and its backside power delivery research has influenced multiple foundries.
By partnering with Lam, IBM gains early access to production-worthy dry resist technology while Lam secures a prestigious research partner and validation vehicle for its Aether platform. The five-year timeframe suggests both parties expect the work to span multiple technology generations.
Impact
This partnership matters because it targets the precise intersection of three critical technologies: High-NA EUV, dry resist, and advanced device architectures. Success could accelerate the industry’s ability to deliver meaningful density and power improvements beyond current roadmaps.
For AI developers and cloud providers, the stakes are concrete. Each successive process node historically delivers 20-30% better power efficiency. At the scale of 100,000-GPU clusters, even modest efficiency gains translate into tens of millions of dollars in annual electricity savings and reduced pressure on power grid infrastructure.
“Accelerating the development of lower power and higher performance transistors that will be critical for AI era.”
The collaboration also highlights the increasing importance of materials science in semiconductor progress. As classical scaling becomes more difficult, breakthroughs in resist chemistry, deposition techniques, and metrology often determine which companies maintain leadership.
What’s Next
The companies have not disclosed specific technical milestones or target production timelines. However, the five-year collaboration suggests initial process validation could occur within 12-24 months, with more complete flow demonstrations potentially ready by 2028-2030.
High-NA EUV tools are already operational at select development sites. The primary bottlenecks remain resist performance, stochastic noise management, and the massive capital investment required to bring the technology to high-volume manufacturing. Successful integration of Lam’s dry resist at IBM’s Albany lab could de-risk adoption for multiple foundries and accelerate the timeline for sub-1nm logic.
Industry observers will watch closely for early benchmark data on line-edge roughness, defect density, and device electrical characteristics once the joint team begins publishing results.
Sources
- IBM Newsroom - IBM and Lam Research Announce Collaboration to Advance Sub-1nm Logic Scaling
- Tom's Hardware - IBM and Lam Research team up on High NA EUV dry resist to push chip scaling past 1nm
- PR Newswire - IBM and Lam Research Announce Collaboration to Advance Sub-1nm Logic Scaling
- HPCwire - IBM and Lam Research Announce Collaboration to Advance Sub-1nm Logic Scaling